<architecture, processor> The sequence of actions that a central processing unit performs to execute each {machine code} instruction in a program. At the beginning of each cycle the CPU presents the value of the program counter on the address bus. The CPU then fetches the instruction from main memory (possibly via a cache and/or a pipeline) via the data bus into the instruction register. From the instruction register, the data forming the instruction is decoded and passed to the control unit which sends a sequence of control signals to the relevant {function units} of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to add them together and writing the result back to a register. The program counter is then incremented to address the next instruction and the cycle is repeated. The fetch-execute cycle was first proposed by {John von Neumann}. (1998-06-25)

The instruction cycle (also known as the fetch–decode–execute cycle, or simply the fetch-execute cycle) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage.

<processor> The four steps which the CPU carries out for each machine language instruction: fetch, decode, execute, and store. These steps are performed by the control unit, and may be fixed in the logic of the CPU or may be programmed as microcode which is itself usually fixed (in ROM) but may be (partially) modifiable (stored in RAM). The fetch cycle places the current program counter contents (the address of the next instruction to execute) on the address bus and reads in the word at that location into the instruction register (IR). In RISC CPUs instructions are usually a single word but in other architectures an instruction may be several words long, necessitating several fetches. The decode cycle uses the contents of the IR to determine which gates should be opened between the CPU's various functional units and busses and what operation the ALU(s) should perform (e.g. add, bitwise and). Each gate allows data to flow from one unit to another (e.g. from register 0 to ALU input 1) or enables data from one output onto a certain bus. In the simplest case ("horizontal encoding") each bit of the instruction register controls a single gate or several bits may control the ALU operation. This is rarely used because it requires long instruction words (such an architecture is sometimes called a {very long instruction word} architecture). Commonly, groups of bits from the IR are fed through decoders to control higher level aspects of the CPU's operation, e.g. source and destination registers, addressing mode and ALU operation. This is known as vertical encoding. One way RISC processors gain their advantage in speed is by having simple instruction decoding which can be performed quickly. The execute cycle occurs when the decoding logic has settled and entails the passing of values between the various function units and busses and the operation of the ALU. A simple instruction will require only a single execute cycle whereas a complex instruction (e.g. subroutine call or one using memory indirect addressing) may require three or four. Instructions in a RISC typically (but not invariably) take only a single cycle. The store cycle is when the result of the instruction is written to its destination, either a register or a memory location. This is really part of the execute cycle because some instructions may write to multiple destinations as part of their execution. (1995-04-13)