Streaming SIMD Extensions - Definition. Was ist Streaming SIMD Extensions
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Was (wer) ist Streaming SIMD Extensions - definition

SIMD INSTRUCTION SET EXTENSION TO THE X86 ARCHITECTURE
SSE1; Katmai New Instructions; Cat my new instructions; Screaming SIMD; XMM0 register; XMM1 register; XMM2 register; XMM3 register; XMM4 register; XMM5 register; XMM6 register; XMM7 register; XMM8 register; XMM9 register; XMM10 register; XMM11 register; XMM12 register; XMM13 register; XMM14 register; XMM15 register; MXCSR register; Streaming SIMD extensions; SSE instructions; XMM register; Internet Streaming SIMD Extensions; SSE 1

Streaming SIMD Extensions         
<architecture> (SSE) Intel Corporation's floating point SIMD extention of their Pentium microprocessor architecture. SSE was formerly know as KNI (Katmai New Instructions). It was introduced with the Pentium III. {Intel Pentium III (http://developer.intel.com/design/pentiumiii/prodbref/)}. ipoem (http://ipoem.com/technology/Docs/pentium4.html). (2003-07-13)
Streaming SIMD Extensions         
In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of Central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!.
Katmai New Instructions         

Wikipedia

Streaming SIMD Extensions

In computing, Streaming SIMD Extensions (SSE) is a single instruction, multiple data (SIMD) instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of central processing units (CPUs) shortly after the appearance of Advanced Micro Devices (AMD's) 3DNow!. SSE contains 70 new instructions (65 unique mnemonics using 70 encodings), most of which work on single precision floating-point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

Intel's first IA-32 SIMD effort was the MMX instruction set. MMX had two main problems: it re-used existing x87 floating-point registers making the CPUs unable to work on both floating-point and SIMD data at the same time, and it only worked on integers. SSE floating-point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers.

SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3 and SSE4. Because it supports floating-point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations.

SSE was originally called Katmai New Instructions (KNI), Katmai being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from their earlier product line, particularly their flagship Pentium II. It was later renamed Internet Streaming SIMD Extensions (ISSE), then SSE. AMD eventually added support for SSE instructions, starting with its Athlon XP and Duron (Morgan core) processors.