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What (who) is Joint Test Action Group - definition

STANDARD SERIAL INTERFACE FOR INTEGRATED CIRCUITS

Wiggler (JTAG); Jtag; 1149.1; IEEE 1149; JTAG connector; JTAG header; CJTAG; Serial Wire Debug; Joint Test Action Group; Test access port; EJTAG; JTAG interface; JTAG port

Joint Test Action Group

<architecture, body, electronics, integrated circuit, standards, testing> (JTAG, or "IEEE Standard 1149.1") A standard specifying how to control and monitor the pins of compliant devices on a printed circuit board. Each device has four JTAG control lines. There is a common reset (TRST) and clock (TCLK). The data line daisy chains one device's TDO pin to the TDI pin on the next device. The protocol contains commands to read and set the values of the pins (and, optionally internal registers) of devices. This is called "boundary scanning". The protocol makes board testing easier as signals that are not visible at the board connector may be read and set. The protocol also allows the testing of equipment, connected to the JTAG port, to identify components on the board (by reading the device identification register) and to control and monitor the device's outputs. JTAG is not used during normal operation of a board. JTAG Technologies B.V. (http://jtag.com/). {Boundary Scan/JTAG Technical Information - Xilinx, Inc. (http://xilinx.com/support/techsup/journals/jtag/)}. {Java API for Boundary Scan FAQs - Xilinx Inc. (http://xilinx.com/products/software/sx/sxfaqs.htm)}. {JTAG Boundary-Scan Test Products - Corelis, Inc. (http://corelis.com/products/scanovrv.html)}. {"Logic analyzers stamping out bugs at the cutting edge", EDN Access, 1997-04-10 (http://ednmag.com/ednmag/reg/1997/041097/08df_02.htm)}. {IEEE 1149.1 Device Architecture - Boundary-Scan Tutorial from ASSET InterTech, Inc. (http://asset-intertech.com/tutorial/arch.htm)}. {"Application-Specific Integrated Circuits", Michael John Sebatian Smith, published Addison-Wesley - Design Automation Cafe (http://dacafe.com/DACafe/EDATools/EDAbooks/ASIC/Book/CH14/CH14.2.htm)}. {Software Debug options on ASIC cores - Embedded Systems Programming Archive (http://embedded.com/97/feat9701.htm)}. {Designing for On-Board Programming Using the IEEE 1149.1 (JTAG) Access Port - Intel (http://developer.intel.com/design/flcomp/applnots/292186.htm)}. {Built-In Self-Test Using Boundary Scan by Texas Instruments - EDTN Network (http://edtn.com/scribe/reference/appnotes/md003e9a.htm)}. (1999-11-15)

JTAG

Joint Test Action Group

JTAG

Joint Test Action Group (Reference: org., Philips, IC)

Wikipedia

JTAG

JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.

JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. The interface connects to an on-chip Test Access Port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.

The Joint Test Action Group formed in 1985 to develop a method of verifying designs and testing printed circuit boards after manufacture. In 1990 the Institute of Electrical and Electronics Engineers codified the results of the effort in IEEE Standard 1149.1-1990, entitled Standard Test Access Port and Boundary-Scan Architecture.

The JTAG standards have been extended by many semiconductor chip manufacturers with specialized variants to provide vendor-specific features.

https://en.wikipedia.org/wiki/JTAG