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instruction queue - translation to russian
METHOD OF IMPROVING INSTRUCTION-LEVEL PARALLELISM
Instruction Prefetch Queue; Superpipelined; Deep pipelining; Pipelined CPU; Prefetch instruction queue; Superpipeline; Pipelined processor; Instruction pipeline
instruction queue
общая лексика
очередь команд
буфер процессора, в который команда попадает после операции выборки и откуда она направляется на соответствующее исполнительное устройство
синоним
queuing
![Commuters at [[Osaka Station]] waiting to board a train. Queues for specific trains are marked by color-coded lines on the platform.](https://commons.wikimedia.org/wiki/Special:FilePath/Osaka Station platform passenger queue 2022-02-03.jpg?width=200 "Commuters at [[Osaka Station]] waiting to board a train. Queues for specific trains are marked by color-coded lines on the platform.")
![1943 [[soup kitchen]] queue in [[Aarhus]], Denmark](https://commons.wikimedia.org/wiki/Special:FilePath/Queue outside a soup kitchen at Klostertorv in Ålborg 1943.jpg?width=200 "1943 [[soup kitchen]] queue in [[Aarhus]], Denmark")
LINE OF PEOPLE WAITING FOR GOODS OR SERVICES ON A FIRST-COME, FIRST-SERVED BASIS, OR AN AREA WHERE SUCH A LINE FORMS
Queue areas; Queueing; Waiting area; Queuing; Waiting in line; Wait in line; Standing in line; Waitlist management; Queue line
waiting area
LINE OF PEOPLE WAITING FOR GOODS OR SERVICES ON A FIRST-COME, FIRST-SERVED BASIS, OR AN AREA WHERE SUCH A LINE FORMS
Queue areas; Queueing; Waiting area; Queuing; Waiting in line; Wait in line; Standing in line; Waitlist management; Queue line
[воен.] выжидательный район (при форсировании водной преграды)
Definition
superpipelined
1. Traditional pipelined architectures have a single
pipeline stage for each of: instruction fetch, instruction
decode, memory read, ALU operation and memory write. A
superpipelined processor has a pipeline where each of
these logical steps may be subdivided into multiple pipeline
stages.
2. Marketese for pipelined.
Wikipedia
Instruction pipelining
In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions processed in parallel.
