indirect address

<processor> An addressing mode found in many processors' instruction sets where the instruction contains the address of a memory location which contains the address of the operand (the "effective address") or specifies a register which contains the effective address. In the first case (indirection via memory), accessing the operand requires two memory accesses - one to fetch the effective address and another to read or write the actual operand. Register indirect addressing requires only one memory access. An indirect address may be indicated in assembly language by an operand in parentheses, e.g. in Motorola 68000 assembly MOV D0,(A0) writes the contents of register D0 to the location pointed to by the address in register A0. Indirect addressing is often combined with pre- or post- increment or decrement addressing, allowing the address of the operand to be increased or decreased by one (or some specified number) either before or after using it. (1994-11-07)

1. <processor, programming> One of a set of methods for specifying the operand(s) for a machine code instruction. Different processors vary greatly in the number of addressing modes they provide. The more complex modes described below can usually be replaced with a short sequence of instructions using only simpler modes. The most common modes are "register" - the operand is stored in a specified register; "absolute" - the operand is stored at a specified memory address; and "immediate" - the operand is contained within the instruction. Most processors also have indirect addressing modes, e.g. "register indirect", "memory indirect" where the specified register or memory location does not contain the operand but contains its address, known as the "effective address". For an absolute addressing mode, the effective address is contained within the instruction. Indirect addressing modes often have options for pre- or post- increment or decrement, meaning that the register or memory location containing the effective address is incremented or decremented by some amount (either fixed or also specified in the instruction), either before or after the instruction is executed. These are very useful for stacks and for accessing blocks of data. Other variations form the effective address by adding together one or more registers and one or more constants which may themselves be direct or indirect. Such complex addressing modes are designed to support access to multidimensional arrays and arrays of data structures. The addressing mode may be "implicit" - the location of the operand is obvious from the particular instruction. This would be the case for an instruction that modified a particular control register in the CPU or, in a stack based processor where operands are always on the top of the stack. 2. In IBM System 370/XA the addressing mode bit controls the size of the effective address generated. When this bit is zero, the CPU is in the 24-bit addressing mode, and 24 bit instruction and operand effective addresses are generated. When this bit is one, the CPU is in the 31-bit addressing mode, and 31-bit instruction and operand effective addresses are generated. ["IBM System/370 Extended Architecture Principles of Operation", Chapter 5., 'Address Generation', BiModal Addressing]. (1995-03-30)