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O que (quem) é Scalable Processor ARChitecture - definição

RISC INSTRUCTION SET ARCHITECTURE

Sun SPARC; Sparc; SPARC International; Scalable Processor ARChitecture; Sun Sparc; Scalable Processor Architecture; Sparc 32; SPARC V7; SPARC V8; SPARC V8E; SPARC V9; SPARCv9; SPARC processor architecture; Silicon secured memory

Scalable Processor ARChitecture

<computer> (SPARC) An instruction set architecture designed by Sun Microsystems for their own use in 1985. Sun was a maker of 680x0-based Unix workstations. Research versions of RISC processors had promised a major step forward in speed but existing manufacturers were slow to introduce a RISC type processor, so Sun went ahead and developed its own, based on the {University of California at Berkley}'s RISC I and RISC II 1980-2. In keeping with their open philosophy, they licenced it to other companies, rather than manufacture it themselves. The evolution and standardisation of SPARC is now directed by the non-profit consortium SPARC International, Inc. SPARC was not the first RISC processor. The AMD 29000 came before it, as did the MIPS R2000 (based on Stanford's design) and Hewlett-Packard Precision Architecture CPU, among others. The SPARC design was radical at the time, even omitting multiple cycle multiply and divide instructions (like a few others), while most RISC CPUs are more conventional. SPARC implementations usually contain 128 or 144 registers, (CISC designs typically had 16 or less). At each time 32 registers are available - 8 are global, the rest are allocated in a "window" from a stack of registers. The window is moved 16 registers down the stack during a function call, so that the upper and lower 8 registers are shared between functions, to pass and return values, and 8 are local. The window is moved up on return, so registers are loaded or saved only at the top or bottom of the register stack. This allows functions to be called in as little as 1 cycle. Like some other RISC processors, reading global register zero always returns zero and writing it has no effect. SPARC is pipelined for performance, and like previous processors, a dedicated condition code register holds comparison results. SPARC is "scalable" mainly because the register stack can be expanded (up to 512, or 32 windows), to reduce loads and saves between functions, or scaled down to reduce interrupt or context switch time, when the entire register set has to be saved. Function calls are usually much more frequent, so the large register set is usually a plus. SPARC is not a chip, but a specification, and so there are various implementations of it. It has undergone revisions, and now has multiply and divide instructions. Most versions are 32 bits, but there are designs for 64-bit and superscalar versions. SPARC was submitted to the IEEE society to be considered for the P1754 microprocessor standard. SPARC(R) is a registered trademark of SPARC International, Inc. in the United States and other countries. [The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]. (1994-11-01)

SPARC

Scalable Processor ARChitecture (Reference: Sun)

SPARC

Standard Planning And Requirement Committee (Reference: ANSI, org.)

Wikipédia

SPARC

SPARC (Scalable Processor Architecture) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s.

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne, and Fujitsu, among others.

The design was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments. Due to SPARC International, SPARC is fully open, non-proprietary and royalty-free.

As of September 2017, the latest commercial high-end SPARC processors are Fujitsu's SPARC64 XII (introduced in 2017 for its SPARC M12 server) and Oracle's SPARC M8 introduced in September 2017 for its high-end servers.

On Friday, September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing the M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts.

Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM-based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and a year later for their mainframe and end-of-support in 2034 "to promote customer modernization".

https://en.wikipedia.org/wiki/SPARC