<architecture> Not synchronised by a shared signal such as clock or semaphore, proceeding independently. Opposite: synchronous. 1. <operating system> A process in a multitasking system whose execution can proceed independently, "in the background". Other processes may be started before the asynchronous process has finished. 2. <communications> A communications system in which data transmission may start at any time and is indicated by a start bit, e.g. EIA-232. A data byte (or other element defined by the protocol) ends with a stop bit. A continuous marking condition (identical to stop bits but not quantized in time), is then maintained until data resumes. (1995-12-08)

<spelling> It's spelled "asynchronous". (1996-12-13)

In telecommunications, asynchronous operation or asynchronous working is where a sequence of operations is executed such that the operations are executed out of time coincidence with any event. It can also be an operation that occurs without a regular or predictable time relationship to a specified event; e.

The primary focus of this article is asynchronous control in digital electronic systems. In a synchronous system, operations (instructions, calculations, logic, etc.

Asynchronous muscles are muscles in which there is no one-to-one relationship between electrical stimulation and mechanical contraction. These muscles are found in 75% of flying insects and have convergently evolved 7-10 times.

Asynchronous circuit (clockless or self-timed circuit) is a sequential digital logic circuit that does not use a global clock circuit or signal generator to synchronize its components. Instead, the components are driven by a handshaking circuit which indicates a completion of a set of instructions.

Asynchronous learning is a general term used to describe forms of education, instruction, and learning that do not occur in the same place or at the same time. It uses resources that facilitate information sharing outside the constraints of time and place among a network of people..

<architecture> A data-driven circuit design technique where, instead of the components sharing a common clock and exchanging data on clock edges, data is passed on as soon as it is available. This removes the need to distribute a common clock signal throughout the circuit with acceptable {clock skew}. It also helps to reduce power dissipation in CMOS circuits because gates only switch when they are doing useful work rather than on every clock edge. There are many kinds of asynchronous logic. Data signals may use either "dual rail encoding" or "data bundling". Each dual rail encoded Boolean is implemented as two wires. This allows the value and the timing information to be communicated for each data bit. Bundled data has one wire for each data bit and another for timing. Level sensitive circuits typically represent a logic one by a high voltage and a logic zero by a low voltage whereas transition signalling uses a change in the signal level to convey information. A speed independent design is tolerant to variations in gate speeds but not to propagation delays in wires; a delay insensitive circuit is tolerant to variations in wire delays as well. The purest form of circuit is delay-insensitive and uses dual-rail encoding with transition signalling. A transition on one wire indicates the arrival of a zero, a transition on the other the arrival of a one. The levels on the wires are of no significance. Such an approach enables the design of fully delay-insensitive circuits and automatic layout as the delays introduced by the layout compiler can't affect the functionality (only the performance). Level sensitive designs can use simpler, stateless logic gates but require a "return to zero" phase in each transition. http://cs.man.ac.uk/amulet/async/. (1995-01-18)